1. Field of the Invention
The present invention generally relates metal oxide semiconductors (MOS) and more specifically to a V-groove metal oxide semiconductor (VMOS) structure having a shallow trench isolation (STI) region.
2. Description of the Related Art
Metal oxide semiconductor field effect transistors (MOSFETs) are typically formed to have active arrays of devices such as in dynamic random access memories (DRAM), read only memories (ROMs), electrically programable read only memories (EPROMs) and other similar devices. In addition, such structures will include support MOSFETs such as drivers, decoders, I/O circuitry and other similar devices. The array MOSFETs require a relatively thick gate oxide when compared to the support MOSFETs.
A relatively thick gate oxide layer increases the maximum wordline boost voltage which can be applied to the array MOSFETs. To the contrary, the support MOSFETs exhibit significantly increased performance as the gate oxide thickness decreases.
Therefore, decreasing the gate oxide thickness increases the performance of the support MOSFETs but decreases charge transfer of efficiency (and degrades the performance) of the array MOSFETs. Therefore, the conventional structures suffer from an inherent trade-off between the gate oxide thickness required for the array MOSFETs and the gate oxide thickness required for the support MOSFETs.
Conventional solutions to the foregoing trade-off problem include a dual gate oxide process where the gate oxide for the array MOSFETs is formed separately from the gate oxide for the support MOSFETs. However, such processing substantially increases the cost of producing the device and further increases the chance for defects. Therefore, there is a need for a single process which selectively forms the gate oxide differently for different devices.
It is, therefore, an object of the present invention to provide a structure and method for simultaneously forming array structures and support structures on a substrate, the method comprising forming the array structures to have a V-groove, forming the support structures to have a planar surface, and simultaneously forming a first oxide in the V-groove and a second oxide in the planar surface, wherein the first oxide is thicker than the second oxide.
The V-groove has at least one surface along a  less than 111 greater than  crystal plane of the substrate and the planar surface has a surface along a  less than 100 greater than  crystal plane of the substrate. The forming of the V-groove comprises performing a crystallographic preferential etch which etches a  less than 111 greater than  crystal plane of the substrate at a different rate than a  less than 100 greater than  crystal plane of the substrate.
The method may further comprise forming a shallow trench isolation region for the active structures, forming a protective layer above the substrate, patterning the protective layer to define the active structures and storage structures, forming conductors in the active structures and the storage structures, and forming wordlines above the conductors, wherein the patterned protective layer aligns the conductors and the wordlines. The forming of the wordlines comprises positioning a mask approximately over the active structures and the storage structures, forming grooves for the wordlines using the mask, and depositing a conductive wordline material in the grooves, wherein the protective layer aligns at least one side of the wordlines and the conductors.
The method may further comprise forming a protective layer above the substrate, forming stripes in the protective layer, and patterning the protective layer to alternately define the active structures and storage structures along the stripes, wherein the stripes align the active structures and the storage structures. The method may further comprise forming a protective layer above the substrate, patterning the protective layer to define the active structures and storage structures, forming trenches for the storage structures in the substrate using the patterned protective layer as a mask, forming storage conductors in the trenches, forming a protective oxide layer over the storage conductor, and forming the V-groove of the active structures using the patterned protective layer.
Additionally, the invention includes a semiconductor device comprising a substrate having V-grooves and planar surfaces, array structures in the V-grooves, support structures in the planar surfaces, a first oxide in the V-grooves and a second oxide in the planar surfaces, wherein the first oxide is thicker than the second oxide.
The V-grooves have at least one surface along a  less than 111 greater than  crystal plane of the substrate and the planar surface has a surface along a  less than 100 greater than  crystal plane of the substrate. The invention may further comprise a shallow trench isolation region for the active structures.
Also, the invention may include a protective layer above the substrate having a protective layer defining the active structures and storage structures, conductors in the active structures and the storage structures; and wordlines above the conductors, wherein the patterned protective layer aligns the conductors and the wordlines. The protective layer aligns at least one side of the wordlines and the conductors.
The invention may further comprise a protective layer above the substrate having stripes, the active structures and storage structures alternating along the stripes, wherein the stripes align the active structures and the storage structures.
The invention takes advantage of a selective oxide growth ability and grows thicker gate oxides of the array MOSFETs on surfaces in V-grooves  less than 111 greater than , while thinner support MOSFET oxides are simultaneously grown on the top  less than 100 greater than  surface. More specifically, with the invention, the gate oxide of the array MOSFETs are grown on  less than 111 greater than  surfaces in V-grooves, while the support MOSFET oxides are grown conventionally on the top  less than 100 greater than  surface. Therefore, the invention can selectively form relatively thin oxide layers for the support MOSFETs and simultaneously form thicker gate oxide layers for the array MOSFETs, thereby increasing device performance and decreasing defects.